|
週次 |
日期 |
單元主題 |
|
第1週 |
03/01 |
Course Overview: syllabus and course overview slide |
|
第2週 |
03/08 |
1. HDL1: Fundamentals of Hardware Description Language
2. Update on DSD Overview slide (v2.1) |
|
第3週 |
03/15 |
HDL2: Logic Design at Register Transfer Level |
|
第4週 |
03/22 |
HDL3: Logic Design with Behavior Coding, Design Verification Tool |
|
第5週 |
03/29 |
HDL4: Testbench Writing, Synthesizable Coding of Verilog |
|
第6週 |
04/05 |
溫書假 |
|
第7週 |
04/12 |
HDL5: Complexity Management, Improving Timing/Area/Power |
|
第8週 |
04/19 |
Synth1: Synthesis Overview and Tool Usage |
|
第9週 |
04/26 |
Synth2: Advanced Topics on Synthesis
計算機結構教材(https://www.dropbox.com/s/jouw3yx4gluvjhd/Course.zip?dl=0) |
|
第10週 |
05/03 |
Midterm |
|
第11週 |
05/10 |
Design Guideline: From Spec to Circuit |
|
第13週 |
05/24 |
TA time for homework and final project |
|
第14週 |
05/31 |
Machine Test |
|
第15週 |
06/07 |
Project Check Point (With Proposal) |
|
第16週 |
06/14 |
Break |
|
第17週 |
06/21 |
Project Presentation |
|
第12-1週 |
05/17 |
MIPS1: Memory Hierarchy (5/17)
A short version of Computer Architecture slide for DSD
|
|
第12-2週 |
05/19 |
MIPS2: Pipelined Architecture of MIPS (5/19: 補課) - 1:30pm in EE2-144 (電二144)
Slide is now in CEIBA
2018/05/19 (六) 1:30pm-4:30pm
電二144 |